1. Field of the Invention
The present invention relates to a timer circuit which counts a set input count value (digital data) in response to an input clock to output an overflow signal or a waveform signal at a time corresponding to the input count value.
2. Description of the Prior Art
Generally speaking, a timer circuit consists of an n-bit counter for counting an n-bit input count value in response to an input clock and an overflow detection circuit for detecting an overflow of this counter to output an overflow signal. A timer circuit having a waveform output function comprises a waveform generator circuit responsive to the overflow signal to output a waveform signal which changes from "1" to "0" or "0" to "1", in addition to the above-mentioned elements. The timer circuit having the waveform output function is structured as shown in FIG. 6. In the figure, reference numeral 1 represents a data bus, 3 an overflow detection circuit, 8 a waveform generator circuit, 9 an n-bit counter, 1a an n-bit input count value, 3a an overflow signal, 7a an input clock, 8a an output waveform signal, and 9a a count value. A timer circuit without a waveform output function is not provided with a waveform generator circuit 8. The n-bit counter 9 receives the the n-bit input count value la from the data bus 1 and counts the value in response to the input clock 7a. Then, the n-bit counter 9 outputs the count value 9a to the overflow detection circuit 3. The overflow detection circuit 3 detects an overflow of the n-bit counter 9 from the count value 9a and outputs the overflow signal 3a to the waveform generator circuit 8, which is responsive to the overflow signal 3a to output the output waveform signal 8a which changes from "1" to "0" or from "0" to "1".
FIG.7 is a waveform diagram illustrating the operation of the conventional timer circuit (same structure as that of FIG. 6) in the case of a 4-bit input count value. In the figure, reference letter (A) represents the waveform of the input clock 7a of the n-bit counter 9 (4-bit counter), (B) the count value 9a of the 4-bit counter 9, (C) the waveform of the overflow signal 3a from the overflow detection circuit 3, and (D) the waveform of the output waveform signal 8a from the waveform generator circuit 8. Next, the operation of the conventional timer circuit (4-bit timer circuit) will be described with reference to FIG. 6 and FIG. 7. A timer value "5" ("0101" in binary code) is first set to the 4-bit counter 9 from the data bus 1. The 4-bit counter 9 counts the timer value "5" upon a fall in the input clock 7a. When the 4-bit counter 9 counts "1" ("0001" in binary code) and "0" ("0000" in binary code), it outputs the count value 9a of "0" to the overflow detection circuit 3. The overflow detection circuit 3 detects an overflow from the count value 9a of "0" and outputs the overflow signal 3a to the waveform generator circuit 8. When the waveform generator circuit 8 has received the overflow signal 3a, it outputs the output waveform signal 8a having a cycle T0 and whose waveform is changed from "1" to "0". The waveform of this output waveform signal 8a has been changed from "0" to "1" at the start of counting by the 4-bit counter 9.
This timer circuit has a minimum decomposition width which is based on the input clock and is decreasing with advances in technology. The reason for this is that when the minimum decomposition width of the timer circuit is reduced, the accuracy, for example, of the overflow signal generated from the counter can be improved. In addition, when the timer having a small minimum decomposition width is used in a power control circuit of a PWM control system, voltage generated from a power supply can be finely controlled. Therefore, in order to achieve these advantages, the frequency of the source input clock must be raised to reduce the minimum decomposition width of the conventional timer circuit.
As described in the foregoing, in the conventional timer circuit, the 4-bit counter 9 counts a set count value upon each fall in the input clock. Therefore, the point where the overflow signal 3a is generated from the overflow detection circuit 3 coincides with the cycle of the input clock 7a (1 to 5 in (A) of FIG. 7), and the minimum decomposition width of the overflow signal coincides with the input clock 7a. Therefore, to reduce the minimum decomposition width, the input clock must be speeded up. In the conventional timer circuit having a waveform generation function, the overflow signal 3a ((c) of FIG. 7) triggers a change in the output waveform signal 8a from "1" to "0" or from "0" to "1". Therefore, the point where the output waveform signal 8a is changed coincides with the cycle of the input clock 7a like the overflow signal 3a. In other words, since the minimum decomposition width of the output waveform signal coincides with the input clock, the input clock must be speeded up to reduce the minimum decomposition width. In this way, in the conventional timer circuit, the input clock needs to be speeded up to reduce the minimum decomposition width, but when the frequency of the input clock is raised, the operation speed of circuit elements such as a transistor incorporated in a circuit needs to be increased. Therefore, the conventional timer has the problem that the entire device must be designed adjusted to the frequency of the input clock in addition to the development of circuit elements.